As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for manufacturing, testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the possibility of manufacturing a defective device. It is also helpful to be able to perform the manufacture, testing and debugging of integrated circuits in an efficient and timely manner.
Locating chip-level defects is an important aspect of the testing and debugging procedure. Emission microscopy has long been used to locate chip-level defects by detecting the energy they emit, e.g., infrared light, heat, etc. Emission images generally contain an image showing the circuitry of the device superimposed with the image of the light emitted by the defect(s) to determine a location of a chip-level defect.
While images originally were formed from frontside emissions, as technology has evolved and circuits have been designed with more and more metallization and interconnection layers, the ability to detect all emissions from the frontside has been hampered since some of the emissions cannot pass through the metallization layers. Thus, a shift has occurred in emission imaging to form the images from the backside of the devices. While backside imaging has had a level of success, special considerations are required for the upside-down manner in which the circuitry must be held, probed, and imaged. Thus, viewing emissions from a single side, frontside or backside, has drawbacks.
Accordingly, a need exists for an improved approach to locating chip-level defects through emission imaging. The present invention addresses such a need.